EECS 6350/8350 MODERN COMMUNICATION II

 

 

 

Final Project Report

 

Modeling , Performance Analysis of Noncoherent 8FSK Modem

 

 

 

 

 

 

 

         Instructor: Dr. Kim

 

         Student :   Shensheng Tang

        

 

 

 

Table of Contents

 

1. Project Description.

2. System Architecture and Block Components.

3. Building Models and Simulations.

3.1 Software tool introduction.

3.2 Building Block Model

3.2.1 Signal Sources.

3.2.2 RS encoder / RS Decoder

3.2.3 Interleaver / Deinterleaver

3.2.4 Convolutional Encoder  / Viterbi Decoder

3.2.5 M-FSK Modulator / Demodulator

3.2.6 Tx Shaping Filter / Rx Shaping Filter

3.2.7 AWGN Channel and Jamming Signal Models

3.2.8 Signal Sink Model

4. Simulation Schemes.

5. Conclusions.

Appendix.

 

 

1. Project Description

In this project, we are required o design one of the most popular digital modulation scheme, 8-PSKmodulator/demodulator using complexenvelope method.

Once the modem is designed based on system parameters given, you are requires to analyze its performance under AWGN and Interference. Final results be shown in terms of various Eb/N0 vs Pb curves.

The following are the basic basic system parameter:

1)      Maximum information data rate (source): Rb=2.4 kbps= 48bits/frame.

2)      Signaling bit: 4bits (1011).

3)      Dummy bit:4bits (0011)

4)      Total bit: 56 bits/frame.

5)      Outer RS code: (9,7) code

6)      Flush bit: 8bits/frame

7)      Interleaver (block): 40*3 bit interver

8)      Inner code (Convolutional): rate 2/3

9)      Coded data bit: 120 bits/frame

10)   Txed data bit: 120 bits/frame

11)  No. of Txed 8-FSK symbol: 40 symbols/frame, 3bits/8-FSK symbol

12)  Tone Spacing (8-FSK): 5KHz

13)  Channel Bandwidth: 45KHz

14)  Total Txed symbol/superframe: 40*50 =2000symbol/s.f

15)  Repeat number: 1(No Diversity)

16)  Based on 14) and 150, symbol rate: 2000symbol/s.f =6000 bits/s.f

 

2. System Architecture and Block Components

A typical communication link includes at least three key elements: a transmitter, a channel, and a receiver. The ability to simulate all three of these elements is required in order to successfully model any end-to-end communication system.

The transmitter and receiver elements can in turn be subdivided into further sub-systems, as shown in the Figure 1 below. These include a data source, an optional data encoder (linear block encoder and convolutional encoder), an interleaver, a modulator, a demodulator, an optional data decoder (linear block decoder and Viterbi decoder), and a signal sink.

 

                           Figure 1. Communication system simulation overview

 

The data source generates the information signal that is intended to be sent to a particular receiver. This signal can be either an analog signal such as speech, or a digital signal such as a binary data sequence. This signal is typically a baseband signal represented by a voltage level. For analog signals, it is often desirable to digitally encode the signal prior to transmission by undergoing a quantization process. This step converts the analog signal into a digital signal.

An encoder can also be used to add redundancy to a digital data stream, in the form of additional data bits, in a way that provides an error correction capability at the receiver. This overall process is referred to as Forward Error Correction (FEC). Among the most popular FEC schemes are convolutional coding, block coding and trellis coding. It is important to note that usually the output bit rate of an encoder is not equal to the input bit rate. To properly distinguish between the two bit rates, the transmitter’s input rate is referred to as the information data rate, while the transmitter output rate is referred to as the channel data rate.

Depending on the type of information signal and the particular transmission medium, different modulation techniques are employed. Modulation refers to the specific technique used to represent the information signal as it is physically transmitted to the receiver. Once the signal is modulated, it is sent through a transmission medium, also known as a channel, to reach the intended receiver. This may be a copper wire, coax cable, or the atmosphere in the case of a radio transmission. To some extent, all channels introduce some form of distortion to the original signal. Many different channel models have been developed to mathematically represent such distortions. A commonly used channel model is the Additive White Gaussian Noise (AWGN) channel. In this channel, noise with uniform power spectral density is assumed to be added to the information signal. Other types of channels include fading channels and multipath channels.

When the transmitted signal reaches the intended receiver, it undergoes a demodulation process. This step is the opposite of modulation and refers to the process required to extract the original information signal from the modulated signal.

When data encoding is included at the transmitter, a data-decoding step must be performed prior to recovering the original data signal. The signal decoding process is usually more complicated than the encoding process and can be very computationally intensive. Efficient decoding schemes, however, have been developed over the years -- one example is the Viterbi decoding algorithm, which is used to decode convolutionally encoded data.

Finally, an estimate of the original signal is produced at the output of the receiver. The receiver’s output port is sometimes referred to as the signal sink. we are usually interested in knowing how well the source information was recreated at the receiver’s output. Several metrics are used by evaluating the success of the data transmission. The most common metric, in the case of digital signals, is the received Bit Error Rate (BER). Other valuable performance indicators include the received Signal to Noise Ratio, Eye Patterns and Phase Scatter Plots, etc.

 

3. Building Models and Simulations

3.1 Software tool introduction

This project including system and blocks is simulated by MATLAB/Simulink. Simulink is a software package for modeling, simulating, and analyzing dynamical systems. It supports linear and nonlinear systems, modeled in continuous time, sampled time, or a hybrid of the two. Systems can also be multirate, i.e., have different parts that are sampled or updated at different rates.

For modeling, Simulink provides a graphical user interface (GUI) for building models as block diagrams, using click-and-drag mouse operations. Simulink includes a comprehensive block library of sinks, sources, linear and nonlinear components, and connectors. We can also customize and create our own blocks if there is no what we want in the library.

Models are hierarchical, they can be built by using both top-down and bottom-up approaches. For example, You can view the system at a high level, then double-click on blocks to go down through the levels to see increasing levels of model detail. This approach provides insight into how a model is organized and how its parts interact. The approach is just like SPW software package of Cadence and COSSAP of Synopsis.

After defining a model, simulation can be start. Using scopes and other display blocks, we can see the simulation results while the simulation is running. In addition, we can change parameters and immediately see what happens. The simulation results can be put in the MATLAB workspace for postprocessing and visualization.

3.2 Building Block Model

3.2.1 Signal Sources

The Random-Integer Generator block generates uniformly distributed random integers in the range [0, M-1], where M is the M-ary number. The M-ary number can be either a scalar or a vector. If it is a scalar, then all output random variables are independent and identically distributed (i.i.d.). If the M-ary number is a vector, then its length must equal the length of the Initial seed; in this case each output has its own

output range. If the Initial seed parameter is a constant, then the resulting noise is repeatable.

Signal source parameters are easily specified by accessing each block’s Setup dialog. For example, the Random-Integer Generator block allows the user to specify the M-ary number (2 for binary, 4 for QPSK, 8 for 8-FSK, etc), Initial seed, Sample time, and Samples per frame.

Because we needs a binary random number generator, so we use a Integer-to-Bit Converter block maps each integer in the input vector to a group of bits in the output vector. If m is the Number of bits per integer parameter, then the input integers must be between 0 and 2m-1. The block maps each integer to a group of m bits, using the first bit as the most significant bit. As a result, the output vector length is m times the input vector length. (we use m = 3 for 8-FSK).

The two blocks are shown below.

 

In the receiver side, we need a Bit-to-Integer Converter block maps groups of bits in the input vector to integers in the output vector. If m is the Number of bits per integer parameter ( we use m=3), then the block maps each group of m bits to an integer between 0 and 2m-1. As a result, the output vector length is 1/m times the input vector length. The block is shown below.

                               

3.2.2 RS encoder / RS Decoder    

The Binary-Input RS Encoder block creates a Reed-Solomon code with message length k and codeword length n. Both n and k can be directly specified in the block mask. n must have the form 2m-1, where m is an integer greater than or equal to 3.

The input and output are binary-valued signals that represent messages and codewords, respectively. The input must contain exactly m*k elements. If it is frame-based, then it must be a column vector. The output is a vector of length m*n.

The m*k input bits represent k integers between 0 and 2m-1, where more significant bits are to the right. Similarly, the m*n output bits represent n integers between 0 and 2m-1. An (n,k) Reed-Solomon code can correct up to floor((n-k)/2) symbol errors in each codeword. The (9,7) RS code can not be used in Simulink, I use (15,12) RS code to replace it in simulation.

The RS encoder model and its detailed diagram are shown below.

 

                        

 

The Binary-Output RS Decoder block recovers a binary message vector from a binary

Reed-Solomon codeword vector. For proper decoding, the parameter values in this block should match those in the corresponding Binary-Input RS Encoder block.

If the Reed-Solomon code has message length k and codeword length n, then n must

have the form 2 m-1 for some integer m greater than or equal to 3.

The input and first output are binary-valued signals that represent codewords and messages, respectively. The input must contain exactly m*n elements. The first output is a vector of length m*k. The second output is the number of errors detected during decoding of the codeword.

The RS decoder model and its detailed diagram are shown below.

 

                     

 

 

3.2.3 Interleaver / Deinterleaver    

The Matrix Interleaver block performs block interleaving by filling a matrix with the input symbols row by row and then sending the matrix contents to the output port column by column.

The Number of rows and Number of columns parameters are the dimensions of the matrix that the block uses internally for its computations. The number of elements of the input vector must be the product of Number of rows and Number of columns. In our project, we use a 40*2 Bit Interleaver to process the 80 bits input data, and set the

Number of rows = 40 and Number of columns = 20 to fit for the following 2/3 rate Convolutional encoder.

The Matrix Deinterleaver block performs block deinterleaving by filling a matrix with the input symbols column by column and then sending the matrix contents to the output port row by row. For proper deinterleavering, the parameter values in this block should match those in the corresponding Matrix Interleaver block.

 

The Matrix Interleaver and Deinterleaver block are shown below.

The output data bits from RS encoder is not matching to the input data bits, we use a Pad block in transmitter side and a Truncation block in receiver side to match the data stream. The two blocks change the size of the input matrix by padding or truncating along the rows, the columns, or both dimensions. The block diagram are shown below.

                    

 

3.2.4 Convolutional Encoder  / Viterbi Decoder    

 

The Convolutional Encoder block encodes a sequence of binary input vectors to produce a sequence of binary output vectors.

If the encoder takes k input bit streams (that is, can receive 2k possible input symbols), then this block's input vector length is L*k for some positive integer L. Similarly, if the encoder produces n output bit streams (that is, can produce 2n possible output symbols), then this block's output vector length is L*n.

There are two ertries to be filled out in this block: Trellis structure and Reset.

Trellis structure contains the trellis description of the convolutional encoder. Reset determines whether and under what circumstances the encoder resets to the all-zeros state before processing the input data. Choices can be None, On each frame, and On nonzero Rst input. The last option causes the block to have a second input port, labeled Rst.

In the project, we use the following encoder with rate 2/3 shown in Figure 2.

 

            Fig 2. Convolutional encoder diagram witj rate 2/3

 

For this encoder, the Constraint Length vector is [3,2] for up and down rows (including information bit and memory bits), and the Code Generator matrix is [2 1 4; 0 2 1] ( in octal form). The command below reveals part of the corresponding trellis structure description of this encoder.

                          trellis = poly2trellis([3 2],[ 2 1 4; 0 2 1])

Viterbi decoder is used to decode convolutionally encoded data. If the convolutional code uses an alphabet of 2n possible symbols, then this block's input vector length is L*n for some positive integer L. Similarly, if the decoded data uses an alphabet of 2k possible output symbols, then this block's output vector length is L*k.

The Convolutional encoder and Viterbi decoder model are shown below.

 

 

 

3.2.5 M-FSK Modulator / Demodulator    

The M-FSK Modulator Baseband block modulates using the M-ary frequency shift keying method (we use 8-FSK in the project). The output is a baseband representation of the modulated signal.

There are several parameters to be set in this block:

The M-ary number parameter, M, is the number of frequencies in the modulated signal; The Frequency separation parameter is the distance, in Hz, between successive frequencies of the modulated signal. If the Phase continuity parameter is set to Continuous, then the modulated signal maintains its phase even when it changes its frequency. If the Phase continuity parameter is set to Discontinuous, then the modulated signal comprises portions of M sinusoids of different frequencies. thus, a change in the input value might cause a change in the phase of the modulated signal.

The input and output for this block are discrete-time signals. The Input type parameter determines whether the block accepts integers between 0 and M-1, or binary representations of integers.

For 8-FSK scheme, the binary data are generated from Convolutional encoder output and every 3 bits of binary data are mapped to an 8FSK symbol according to the constellation specification.

 

                

The M-FSK Demodulator Baseband block demodulates a signal that was modulated using the M-ary frequency shift keying method. The input is a baseband representation of the modulated signal. The input and output for this block are also discrete-time signals. The input can be either a scalar or a frame-based column vector.

The outputs can be Binary or Integer outputs. If the Output type parameter is set to Integer, then the block outputs integers between 0 and M-1. If the Output type parameter is set to Bit and the M-ary number parameter has the form 2k for some positive integer k, then the block outputs binary representations of integers between 0 and M-1.

The 8-FSK Modulator / Demodulator model are shown below.

                      

 

3.2.6 Tx Shaping Filter / Rx Shaping Filter    

We use Square Root Cosine Filter as Tx Shaping Filter and Rx Shaping Filter. The design specification and relative diagram are as follows:

·     Generated complex symbols are pulse shaped by this square root cosine filter.

·     The attenuation at cut-off frequency is fixed at 6dB (half the passband gain).

·     Set the sampling frequency (Fs) to 200000 Hz.

·     Thus the sampling frequency is 4 times the maximum frequency corresponding to the pulse which satisfies the nyquist criterion.

·     Choose the cut-off frequency Fc is at 50000Hz. Bandwidth is 45KHz.

·     Choose the filter order as 10.

The following are some design results:

 

                                                 

   

 

The Tx Shaping Filter and Rx Shaping Filter blocks are shown below.

 

 

3.2.7 AWGN Channel and Jamming Signal Models    

3.2.7.1 AWGN Channel Model

The AWGN Channel block adds white Gaussian noise to a real or complex input signal. When the input signal is real, this block adds real Gaussian noise and produces a real output signal. When the input signal is complex, this block adds complex Gaussian noise and produces a complex output signal. This block inherits its sample time from the input signal.

This block uses a Random Source block to generate the noise. The Initial seed parameter in this block initializes the noise generator. Initial seed can be either a scalar or a vector whose length matches the number of channels in the input signal. The AWGN channel model and its detailed structure are shown below.

                 

 

3.2.7.2 Jamming Signal Models    

·        Partial-band Noise Jammer

It consists of noise whose total power is evenly spread over some frequency band that is a subset of the total spread bandwidth. The jammer power spectral density is given by the ratio of the jammer power to the jammed bandwidth.

   , where  

The Partial-band Noise Jammer model and its detailed structure are shown below.

·        Multi-tone Jammer

It transmits more than one narrow-band sinusoidal signals. These are spread across the desired bandwidth and are present all of the time but do not occupy the entire required spectrum. A single tone jammer has the form

                               

A multi-tone jammer divides its total power J, into distinct , equal-power, random-phase continuous wave tones. Multi-tone jammers using Nt equal power tones can be described by

                             

where all phases are assumed to be independent and uniformly distributed over (0,2π). The multi-tone jammer model and its detailed structure are shown below.

 

                                          

3.2.8 Signal Sink Model    

We use the Error Rate Calculation block and the Display block to construct the signal sink model.

The Error Rate Calculation block compares input data from a transmitter with input data from a receiver. It calculates the error rate as a running statistic, by dividing the total number of unequal pairs of data elements by the total number of input data elements from one source. This block can be used to compute either symbol or bit error rate, because it does not consider the magnitude of the difference between input data elements. If the inputs are bits, then the block computes the bit error rate. If the inputs are symbols, then it computes the symbol error rate.

The Display block shows the value of its input. We use it to display the final results of the bit error rate and symbol error rate.

The two blocks are shown below.

4. Simulation Schemes

 

This basic simulation scheme use random signal generator, 8-FSK Modem, Tx/Rx Shaping Filter, Signal Sink to build a system model under AWGN or back to back.

1)      When using back-to-back test without AWGN noise, no error occurs.

 

2)      When adding AWGN, see Scheme 1, we got the following error curves compared to theoretical result with 8-FSK. The basic 8FSK scheme is shown as follows.

 

 

In the following simulation result diagram, BER denotes bit error rate of 8-FSK simulation, SER denotes symbol error rate of 8-FSK simulation, Pe denotes the theoretical upper bound of 8-FSK.

 

 

3)      When adding FEC under 2), see Scheme 2, we got the following error curves compared to the  result of 2) . The simulation result is shown below.

The basic 8FSK scheme with FEC models is shown as follows.

 

4)      When adding Jamming interference under 3), we got the following BER curves.

The following are the simulation results and simulation scheme for partial band jamming and multi-tone jamming, respectively.

 

 

 

 

 

 

Simulation Results:

 

·        Symbol/Bit Error Probability for basic 8-FSK scheme with FEC become worse when adding Jamming interferences. It seems that multi-tone jamming cause larger interference that partial band jamming.

 

5. Conclusions

 

In this project, we use MATLAB/Simulink to build block models and combine them together to get a communication system. And simulate the basic 8FSK scheme under AWGN, adding FEC case, adding Jamming interferences. The simulation results clearly agree with the theoretical concept. From this project, we get a further insight to modeling and simulating communication system.

 

Appendix

See the files in the diskette attached.

comm_basic.mdl,

comm_fec.mdl,

comm_MTJ.mdl,

comm_PBNJ.mdl,

PBNJammer.mdl,

MTJammer.mdl.